1. Field of the Invention
The present invention relates to a solid-state imaging device, an analogue-digital converting method in the solid-state imaging device, and an imaging apparatus and, more specifically, to a solid-state imaging device configured to convert an analogue signal outputted from a unit pixel via a column signal line into a digital signal and read the digital signal, an analogue-digital converting method in the solid-state imaging device and an imaging apparatus in which the solid-state imaging device is employed as an imaging device.
In recent years, a CMOS image sensor including a column parallel Analogue-Digital Converter (hereinafter, referred to as “ADC”), in which ADCs are arranged on a column-to-column basis in a row-column (matrix) array of unit pixels, mounted thereon has been reported (for example, see W. Yang et. al, “An Integrated 800×600 CMOS Image System” ISS CC Digest of Technical Papers, pp. 304-305, February 1999).
2. Description of the Related Art
FIG. 8 is a block diagram showing a configuration of a CMOS image sensor 100 including a column parallel ADC mounted thereon according to the related art.
In FIG. 8, a unit pixel 101 includes a photodiode and an in-pixel amplifier, and constitutes a pixel array block 102 by being arranged two-dimensionally in a row and column array. In the row-column pixel arrangement in the pixel array block 102, row control lines 103 (103-1, 103-2, . . . ) are wired on a row-to-row basis and column signal lines 104 (104-1, 104-2, . . . ) are wired on a column-to-column basis. Control of a row address and a row scanning in the pixel array block 102 is performed by a row scanning circuit 105 via the row control lines 103-1, 103-2, . . . .
ADCs 106 are arranged for the respective column signal lines 104-1, 104-2, . . . and constitute a column processing block (column parallel ADC block) 107 on one side of the column signal lines 104-1, 104-2, . . . . A Digital-Analogue Converter (hereinafter, referred to as “DAC”) 108 for generating reference voltages RAMP of a RAMP waveform and a counter 109 for counting time period during which a comparing operation is performed by a comparator 110, described later, by performing a counting operation synchronously with a clock CK of a predetermined cycle are also provided for the respective ADCs 106.
Each ADC 106 includes the comparator 110 for comparing an analogue signal obtained from the unit pixel 101 in a selected row via the column signal lines 104-1, 104-2, . . . with the reference voltage RAMP generated by the DAC 108 for each column control line 103-1, 103-2, . . . , and a memory unit 111 for retaining a counted value of the counter 109 in response to the compared result outputted from the comparator 110, and has a function to convert an analogue signal provided from the unit pixel 101 into an N-bit digital signal.
Control of a column address and a column scanning for each ADC 106 of the column processing block 107 is performed by a column scanning circuit 112. In other words, the N-bit digital signals which are AD-converted by the respective ADCs 106 are read by a horizontal output line 113 of 2N bit in width in sequence by column scanning by the column scanning circuit 112, and are transmitted to signal processing circuit 114 by the horizontal output line 113. The signal processing circuit 114 includes 2N sense circuits corresponding to the horizontal output line 113 of 2N bit in width, a subtract circuit and an output circuit.
A timing control circuit 115 generates clock signals or timing signals used for the operations of the row scanning circuit 105, the ADC 106, the DAC 108, the counter 109 and the column scanning circuit 112 on the basis of a master clock MCK, and supplies these clock signals or the timing signals to the corresponding circuit member.
Referring now to a timing chart in FIG. 9, an operation of the CMOS image sensor 100 according to the related art configured as described above will be described below.
After a first reading operation from the unit pixels 101 of a certain selected row to the column signal lines 104-1, 104-2, . . . is stabilized, the reference voltage RAMP of the RAMP waveform is applied from the DAC 108 to the comparators 110. Consequently, the comparators 110 compare signal voltages Vx of the column signal lines 104-1, 104-2, . . . and the reference voltage RAMP. When the reference voltage RAMP and the signal voltages Vx become the same during this comparing operation, polarities of outputs Vco from the comparators 110 are inverted. In response to the reception of the inverted outputs from the comparators 110, a count value N1 of the counter 109 corresponding to a comparison period of the comparators 110 is retained in the memory unit 111.
In this first reading operation, a reset component ΔV of the unit pixel 101 is read. The reset component ΔV contains fixed pattern noise which varies from the unit pixel 101 to the unit pixel 101 as an offset. However, since the variation in reset component is generally small and a reset level is common for all the pixels, the signal voltage Vx of the column signal line 104 at the first reading is almost known. Therefore, at the first reading of the reset component ΔV, the comparison period of the comparator 110 can be shortened by adjusting the reference voltage RAMP of the RAMP waveform. In this related art, the reset component ΔV is compared during a count period (128 clocks) which corresponds to 7 bits.
In a second reading operation, the signal component corresponding to the amount of incident light is read for each unit pixel 101 in addition to the reset component ΔV in the same operation as in the case of the first reading operation. In other words, after the second reading operation from the unit pixels 101 of the certain selected row to the column signal lines 104-1, 104-2, . . . is stabilized, the reference voltage RAMP of the RAMP waveform is provided from the DAC 108 to the comparators 110. Consequently, the comparators 110 compare the signal voltages Vx of the column signal lines 104-1, 104-2, . . . and the reference voltage RAMP.
Simultaneously with provision of the reference voltage RAMP to the comparators 110, the counter 109 performs the second counting operation. Then, when the reference voltage RAMP and the signal voltages Vx become the same during the second comparing operation, the polarities of the outputs Vco from the comparators 110 are inverted. In response to the reception of the inverted outputs from the comparators 110, a count value N2 of the counter 109 corresponding to the comparison period of the comparators 110 is retained in the memory unit 111. At this time, the first count value N1 and the second count value N2 are retained in the different places in the memory unit 111.
After completion of the series of AD converting operations described above, the N-bit digital signals of the first time and the second time retained in the memory unit 111 are supplied to the signal processing circuit 114 via the 2N horizontal output lines 113 by the column scanning by the column scanning circuit 112, are applied with subtracting process of (second signal)−(first signal) in the subtract circuit (not shown) in the signal processing circuit 114, and are outputted toward an outside. Subsequently, by repeating the same operation for each row in sequence, a two-dimensional image is generated.